Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof

ABSTRACT

A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls of the two isolation structures. The two dielectric spacers are spaced from one another at a distance that defines a gate width which is beyond lithography limit. A tunnel dielectric and a floating gate are provided on substrate and confined between the two dielectric spacers. The floating gate has a smaller bottom surface area relative to its top surface area and has a surface substantially coplanar with a surface of the isolation structures. On the coplanar surface, an inter-gate dielectric and a control gate are provided. Optionally, a lightly doped region is provided beside the floating gate  118  and within the substrate. A manufacturing method for forming such memory device is also disclosed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a nonvolatilesemiconductor memory device such as an EPROM (erasable programmable readonly memory), EEPROM (electrically erasable programmable read onlymemory) and a flash memory. The present invention also relates to amethod of manufacturing such a nonvolatile semiconductor memory device.

[0003] 2. Description of the Related Arts

[0004] High-density nonvolatile memory devices have been receiving muchattention for application in many fields. One of the most importantfactors is the low cost of the reduced size of each memory cell.However, it is very difficult to shrink the cell size in the fabricationof nonvolatile memory cells when the conventional local oxidation(LOCOS) isolation technique is used. The isolation structure formed bythis technique has a very large dimension and thus limits theminiaturization of the memory cells.

[0005] Another isolation technique called shallow trench isolation (STI)has been introduced to the fabrication of nonvolatile memory devices toreduce the cell size. The conventional field oxides are replaced by STIstructures so that the device integration can be effectively improved.However, as component dimensions continue to shrink, the surface area offloating gates also shrinks. This leads directly to a decrease incapacitance of the effective capacitor formed between the floating gatelayer and the control gate layer. This decrease in effective capacitanceresults in a reduction of the capacitive coupling ratio, which is aparameter that describes the coupling to floating gate of the voltageapplied to control gate. The poorly-coupled voltage to floating gatelimits the programming and accessing speed characteristics of the memorydevice.

[0006] The capacitive coupling ratio Cp is defined by:${Cp} = \frac{Ccf}{{Ccf} + {{Cf}\quad s}}$

[0007] where Ccf is capacitance between the control gate and thefloating gate; and Cfs is capacitance between the floating gate and thesemiconductor substrate.

[0008] In order to gain programming and accessing speeds in nonvolatilememories, many attempts have been done to increase the coupling ratio.It can be understood from the above equation that when the capacitanceCcf between the control gate and the floating gate increases, thecoupling ratio Cp increases. Therefore, the coupling ratio Cp isgenerally increased by increasing the capacitor area between thefloating gate and control gate, which increases the capacitance Ccf, andtherefore the coupling ratio Cp. For example, U.S. Pat. No. 6,171,909discloses a method for forming a stacked gate of a flash memory cell.The coupling ratio of the stacked gate is increased by forming aconductive spacer. The conductive spacer, which is a portion of thefloating gate, increases the capacitor area between the floating gateand control gate.

[0009] In the present invention, a nonvolatile semiconductor memorydevice with an increased coupling ratio is disclosed. This isaccomplished by providing a reduced size floating gate which reduces thecapacitance Cfs between the floating gate and the semiconductorsubstrate. The effect is the same as increasing the capacitance Ccfbetween the control gate and the floating gate.

SUMMARY OF THE INVENTION

[0010] An object of the invention is to provide a nonvolatilesemiconductor memory device having an increased capacitive couplingratio.

[0011] Another object of the invention is to provide a nonvolatilesemiconductor memory device having an reduced size floating gate with agate width beyond lithography limit.

[0012] A further object of the invention is to provide a method forforming a nonvolatile semiconductor memory device having an increasedcapacitive coupling ratio.

[0013] A yet further object of the invention is to provide a method forforming a nonvolatile semiconductor memory device having an reduced sizefloating gate with a gate width beyond lithography limit.

[0014] An important feature of the invention is to provide twodielectric spacers on a pair of opposing sidewalls of “RAISED” isolationstructures that protrude over a substrate. The dielectric spacerseffectively decrease the dimension of the floating gate as well as thefloating gate width. This reduces the capacitance Cfs between thefloating gate and the semiconductor substrate, and therefore, increasesthe capacitive coupling ratio.

[0015] According to an aspect of the invention, there is provided anonvolatile memory device including two isolation structures protrudingabove a substrate; two dielectric spacers disposed on a pair of opposingsidewalls of the two isolation structures; a tunnel dielectric and afloating gate provided on the substrate and confined between the twodielectric spacers; and a control gate electrode formed on the floatinggate with an inter-gate dielectric interposed therebetween.

[0016] According to another aspect of the invention, there is provided anonvolatile memory device including two isolation structures protrudingabove a substrate; two dielectric spacers disposed on a pair of opposingsidewalls of the two isolation structures, the two dielectric spacersbeing spaced from one another at a distance that defines a gate widththerebetween; a tunnel dielectric and a floating gate provided on thesubstrate and confined between the two dielectric spacers, the floatinggate having a surface substantially coplanar with a surface of theisolation structures; and an inter-gate dielectric and a control gateformed on the coplanar surfaces of the floating gate and the isolationstructures.

[0017] According a further aspect of the invention, there is provided amethod for forming a nonvolatile memory device comprising the steps offorming two isolation structures protruding above a substrate; formingtwo dielectric spacers on a pair of opposing sidewalls of the twoisolation structures; forming a tunnel dielectric layer and a floatinggate layer on the substrate and confined between the two dielectricspacers on the substrate; and sequentially forming an inter-gatedielectric layer and a control gate layer over said substrate.

[0018] According a yet further aspect of the invention, there isprovided a method for forming a nonvolatile memory device comprising thesteps of forming a mask layer on a semiconductor substrate; patterningthe mask layer and the substrate to form trenches in the substrate;filling the trenches with isolation oxides that protrude above thesubstrate; removing the mask layer to leave a gate opening in betweenthe isolation oxides; forming two dielectric spacers on a pair ofopposing sidewalls of the isolation oxides, the two dielectric spacersbeing spaced from one another at a distance that defines a gate widththerebetween; forming a tunnel dielectric layer on the substrate andbetween the two dielectric spacers; forming a floating gate layer on thetunnel dielectric layer and completely filling the gate opening;planarizing the floating gate layer to form a surface substantiallycoplanar with a surface of the isolation structures; and sequentiallyforming an inter-gate dielectric layer and a control gate layer on thecoplanar surfaces of the floating gate and the two isolation structures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features, and advantages of thepresent invention will become apparent from the following detaileddescription of preferred embodiments of the invention explained withreference to the accompanying drawings, in which:

[0020] FIGS. 1-6 are cross-sectional views illustrating the steps forfabricating a nonvolatile memory device according to a preferredembodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] There will now be described an embodiment of this invention withreference to the accompanying drawings. FIG. 1 shows a semiconductorsubstrate 100 where trenches 106 are formed through a mask layer 105.The mask layer 105 preferably has a thickness between about 200 and 3500Å, which can be a monolayer or stack dielectric layer. The mask layer105 preferably includes a pad oxide layer 102 and a thick nitride layer104 as shown. The pad oxide layer 102 can be formed by thermal oxidationor by an atmospheric or low pressure chemical vapor deposition (LPCVD)process as is well known. The silicon nitride layer 104 is usuallyformed by reacting dichlorosilane (SiCl₂H₂) with ammonia (NH₃) throughan LPCVD process. The nitride layer 104 and the pad oxide layer 102 arethen dry etched using a photoresist pattern as an etching mask whichprotects all areas on which active devices will later be formed. Theetching is further carried into the substrate 100 to form shallowtrenches 106 with a predetermined depth. The photoresist pattern isremoved after using it to define active regions.

[0022] The inside walls of the trenches 106 are then lined with an oxidelayer (not shown) by thermal growth. Subsequently, the trenches 106 arefilled with isolation oxide using the method of high density plasma(HDP) deposition or LPCVD, thus forming “RAISED” shallow trenchisolation (STI) 108 as shown in FIG. 2 Next, the substrate is subjectedto chemical-mechanical polishing (CMP).

[0023] Referring to FIG. 3, the nitride layer 104 is removed, and a gateopening 110 is left behind. Nitride removal can be accomplished by usingphosphoric acid (H₃PO₄). The removal of the nitride layer 104 leaves agate opening 110 in between two isolation oxides 108 that protrude overthe substrate 100. In the gate opening 110, the floating gate of thepresent invention will later be formed. The pad oxide layer 102underlying the nitride layer 104 may also be removed by wet etch.However, it is more preferably in the present invention to preserve thepad oxide layer 102 until a dielectric spacer is later formed. The padoxide layer 102 can serve as a protective layer of the underlyingsubstrate as will become apparent below.

[0024] Referring to FIG. 4, as a main feature and a key aspect of thepresent invention, two dielectric spacers 112 are formed on opposingsidewalls of the isolation oxide 108. The dielectric spacers 112 reducethe dimension of the gate opening 110 and defines a gate width Wtherebeween that is smaller than can be directly fabricated by thedesign rule of fabrication equipment. The dielectric spacers can beformed by depositing a dielectric layer conformally over the substrate100 and the isolation oxide 108, followed by anisotropically etchingback. The pad oxide layer 102, if not removed, serves as a protectivelayer to prevent defects in the substrate 100 that may be generatedduring the etching for forming the dielectric spacers 112. The width ofdielectric spacers is used to define the gate width W. The dielectricspacers 112 may have a width between about 100 to 2000 Å, depending onthe dimension of the floating gate to be formed. The materials used toform the dielectric spacer may be silicon oxide or silicon nitride. Asanother key aspect of the present invention, the dielectric spacer ispreferably formed of doped dielectric such as doped silicon nitride ordoped silicon oxide. As will become apparent below, a lightly dopedregion will be formed during the subsequent thermal process if thespacers 112 are formed of doped dielectric.

[0025] Next, the pad oxide layer 102, if any, is removed by wet etch. Atunnel dielectric 114 is formed between the sidewall spacers 112 asshown in FIG. 5. It is preferably formed by a thermal oxidation processat a temperature between about 750° C. to 950° C. The thermal oxidationconcurrently creats a lightly doped region 116 in substrate beneath thedoped spacers 112 due to diffusion of impurities from the doped spacer112. The lightly doped region 116 prevents the memory device fromnon-gate channel inversion and improves the threshold voltage (Vt)stability. Alternatively, the tunnel dielectric 112 can be formed by anatmospheric or low pressure chemical vapor deposition (LPCVD) process asis well known.

[0026] Subsequently, a first conductive layer of a thickness between 500and 3500 Å is deposited as a blanket layer over the tunnel dielectric114 and completely filling the gate opening 110. The first conducivelayer is preferably formed of doped polysilicon, doped amorphoussilicon, or metal. The blanket layer is then planarized by plasma etchor by chemical-mechanical polishing to the surface of the isolationoxide 108, resulting in a floating gate structure 118 confined betweentwo isolation structures 108. This planarization also creates a coplanarsurface of the floating gate 118 and the isolation oxides 108. As shownin FIG. 5, the dielectric spacers 112 create a smaller geometric areabetween the floating gate 118 and the semiconductor substrate 100, whichreduces the capacitance between the floating gate and the substrate, andtherefore increases the capacitive coupling ratio. The floating gatewidth which is beyond lithography limit is defined by subtracting twicethe spacer width from the width of the gate opening.

[0027] Next, as shown in FIG. 6, an inter-gate dielectric layer 120 anda second conductive layer 122 for serving as a control gate layer aresequentially formed over the coplanar surface of the floating gate 118and the isolation oxides 108. The inter-gate dielectric layer 120 istypically composed of oxide/nitride/oxide (ONO), nitride/oxide (NO), orTa₂O₅. The second conductive layer 122 is typically made of dopedpolysilicon or polycide. Finally, a masking and etching process isperformed to define a control gate from the second conductive layer 122.Thus, a nonvolatile memory device with a reduced size floating gate andan increased coupling ratio is fabricated.

[0028] As shown in FIG. 6, the nonvolatile memory device according tothe invention includes at least two isolation structures 108 protrudingabove a semiconductor substrate 100. Two dielectric spacers 112,preferably doped spacers, are disposed on a pair of opposing sidewallsof the two isolation structures 108. The two dielectric spacers 112 arespaced from one another at a distance that defines a gate widththerebetween which is beyond lithography limit. A tunnel dielectric 144and a floating gate 118 are provided on the substrate and confinedbetween the two dielectric spacers 112. The floating gate 118 has asmaller bottom surface area relative to its top surface area and has asurface substantially coplanar with a surface of the isolationstructures 108. On the coplanar surface, an inter-gate dielectric 120and a control gate 122 are provided. Optionally, a lightly doped region116 is provided beside the floating gate 118 and within the substrate100.

[0029] Accordingly, the present invention provides a technique,including a device and method, for a reduced size floating gate for anonvolatile memory device. This reduced floating gate has gate widthbeyond lithography limit which reduces the capacitance between thefloating gate and the substrate and results in an increased capacitivecoupling ratio.

[0030] While the invention has been particularly shown and describedwith reference to the preferred embodiment thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A nonvolatile memory device, comprising: twoisolation structures protruding above a substrate; two dielectricspacers disposed on a pair of opposing sidewalls of said two isolationstructures; a tunnel dielectric and a floating gate provided on saidsubstrate and confined between said two dielectric spacers; and acontrol gate electrode formed on said floating gate with an inter-gatedielectric interposed therebetween.
 2. The nonvolatile memory device asclaimed in claim 1, wherein said dielectric spacers have a width betweenabout 100 and 2000 Å.
 3. The nonvolatile memory device as claimed inclaim 1, wherein said dielectric spacers are formed of silicon oxide orsilicon nitride.
 4. The nonvolatile memory device as claimed in claim 1,wherein said sidewall spacer are formed of doped silicon oxide or dopedsilicon nitride.
 5. The nonvolatile memory device as claimed in claim 1,wherein said floating gate is formed of a material selected from thegroup consisting of doped polysilicon, doped amorphous silicon, andmetal.
 6. The nonvolatile memory device as claimed in claim 1, whereinsaid floating gate is formed of doped polysilicon.
 7. The nonvolatilememory device as claimed in claim 1, wherein said control gate is formedof a material selected from the group consisting of doped polysiliconand polycide.
 8. The nonvolatile memory device as claimed in claim 1,wherein said floating gate is formed of doped polysilicon.
 9. Thenonvolatile memory device as claimed in claim 1, further comprising alightly doped region provided beside said floating gate and within saidsubstrate.
 10. The nonvolatile memory device as claimed in claim 1,wherein said floating gate has a smaller bottom surface area relative toits top surface area.
 11. A nonvolatile memory device, comprising: twoisolation structures protruding above a substrate; two dielectricspacers disposed on a pair of opposing sidewalls of said two isolationstructures, said two dielectric spacers being spaced from one another ata distance that defines a gate width therebetween; a tunnel dielectricand a floating gate provided on said substrate and confined between saidtwo dielectric spacers, said floating gate having a surfacesubstantially coplanar with a surface of said isolation structures; andan inter-gate dielectric and a control gate formed on the coplanarsurfaces of said floating gate and said isolation structures.
 12. Thenonvolatile memory device as claimed in claim 11, wherein saiddielectric spacers have a width between about 100 and 2000 Å.
 13. Thenonvolatile memory device as claimed in claim 11, wherein saiddielectric spacers are formed of silicon oxide or silicon nitride. 14.The nonvolatile memory device as claimed in claim 11, wherein saidsidewall spacers are formed of doped silicon oxide or doped siliconnitride.
 15. The nonvolatile memory device as claimed in claim 11,further comprising a lightly doped region provided beside said floatinggate and within said substrate.
 16. The nonvolatile memory device asclaimed in claim 11, wherein said floating gate has a smaller bottomsurface area relative to its top surface area.
 17. The nonvolatilememory device as claimed in claim 11, wherein said two sidewall spacersdefines a gate width that is beyond lithography limit.
 18. A method forforming a nonvolatile memory device, comprising the steps of: formingtwo isolation structures protruding above a substrate; forming twodielectric spacers on a pair of opposing sidewalls of said two isolationstructures; forming a tunnel dielectric layer and a floating gate layeron said substrate and confined between said two dielectric spacers onsaid substrate; and sequentially forming an inter-gate dielectric layerand a control gate layer over said substrate.
 19. The method as claimedin claim 18, wherein said dielectric spacers have a width between about100 and 2000 Å.
 20. The method as claimed in claim 18, wherein saiddielectric spacers are formed of silicon oxide or silicon nitride. 21.The method as claimed in claim 18, wherein said sidewall spacer areformed of doped silicon oxide or doped silicon nitride.
 22. The methodas claimed in claim 18, wherein said floating gate is formed of amaterial selected from the group consisting of doped polysilicon, dopedamorphous silicon, and metal.
 23. The method as claimed in claim 18,wherein said floating gate is formed of doped polysilicon.
 24. Themethod as claimed in claim 18, wherein said control gate is formed of amaterial selected from the group consisting of doped polysilicon andpolycide.
 25. The method as claimed in claim 18, wherein said floatinggate is formed of doped polysilicon.
 26. The method as claimed in claim18, further comprising forming a lightly doped region beside saidfloating gate and within said substrate.
 27. The method as claimed inclaim 18, wherein said floating gate has a smaller bottom surface arearelative to its top surface area.
 28. A method for forming a nonvolatilememory device, comprising the steps of: forming a mask layer on asemiconductor substrate; patterning said mask layer and said substrateto form trenches in said substrate; filling said trenches with isolationoxides that protrude above said substrate; removing said mask layer toleave a gate opening in between said isolation oxides; forming twodielectric spacers on a pair of opposing sidewalls of said isolationoxides, said two dielectric spacers being spaced from one another at adistance that defines a gate width therebetween; forming a tunneldielectric layer on said substrate and between said two dielectricspacers; forming a floating gate layer on said tunnel dielectric layerand completely filling said gate opening; planarizing said floating gatelayer to form a surface substantially coplanar with a surface of saidisolation structures; and sequentially forming an inter-gate dielectriclayer and a control gate layer on said coplanar surfaces of saidfloating gate and said two isolation structures.
 29. The method asclaimed in claim 28, wherein said mask layer comprises a stack of a padoxide layer and a silicon nitride layer.
 30. The method as claimed inclaim 28, wherein said mask layer has a thickness between about 200 and3500 Å.
 31. The method as claimed in claim 28, wherein said dielectricspacers have a width between about 100 and 2000 Å.
 32. The method asclaimed in claim 28, wherein said dielectric spacers are formed ofsilicon oxide or silicon nitride.
 33. The method as claimed in claim 28,wherein said sidewall spacers are formed of doped silicon oxide or dopedsilicon nitride.
 34. The method as claimed in claim 28, furthercomprising forming a lighted dope region beside said floating gate andwithin said substrate.
 35. The method as claimed in claim 28, whereinsaid floating gate has a smaller bottom surface area relative to its topsurface area.
 36. The method as claimed in claim 28, wherein said twosidewall spacers defines a gate width that is beyond lithography limit.37. A method for forming a nonvolatile memory device, comprising thesteps of: forming a pad oxide layer and a silicon nitride layer on asemiconductor substrate; patterning said silicon nitride layer, said padoxide layer and said substrate to form trenches in said substrate;filling said trenches with isolation oxides that protrude above saidsubstrate; removing said silicon nitride layer to leave a gate openingbetween said isolation oxides; forming two doped dielectric spacers on apair of opposing sidewalls of said isolation oxides, said two dopeddielectric spacers being spaced from one another at a distance thatdefines a gate width therebetween; removing said pad oxide layer;forming a tunnel dielectric layer between said two doped dielectricspacers and concurrently forming a lighted doped region beneath said twodoped dielectric spacers by thermal oxidation; forming a floating gatelayer on said tunnel dielectric layer and completely filling said gateopening; planarizing said floating gate layer to form a surfacesubstantially coplanar with a surface of said isolation structures; andsequentially forming an inter-gate dielectric layer and a control gatelayer on said coplanar surfaces of said floating gate and said twoisolation structures.